Digital data is commonly transmitted and received between different data processing systems via electronic signals. Many data transmission formats include a clock that is separately transmitted with the data. Other data transmission formats are self-clocking, because every clock period includes a signal transition. Many other types of data transmissions are not self-clocking because they encode data as a series of high and low pulses of varying duration. Consecutive high or low pulses do not produce a transition between the pulses, so that pulses of varying duration are produced.
In order to recover a clock from an input signal, it is known to provide clock recovery circuits and methods. See for example, U.S. Pat. No. 5,671,258 to Burns et al. entitled "Clock Recovery Circuit and Receiver Using Same", and U.S. Pat. No. 5,689,692 to MacTaggart et al. entitled "Method and Apparatus for Decoding an Encoded NRZ Signal".
Clock recovery can become complicated for variable frequency input data. For example, when using Asynchronous Transfer Mode (ATM) data transmission formats, data may be transmitted at either 32 megabits per second (Mbps) or 64 Mbps. Since ATM data may include an extra bit for every four consecutive zero bits, these transmission rates generally correspond to effective data rates of about 25 Mbps and about 50 Mbps respectively.
Clock recovery circuits and methods often include a phase locked loop to lock onto a clock frequency. As is well known to those having skill in the art, a phase locked loop generally includes a reference clock or oscillator. Accordingly, when recovering clock signals from multiple frequency input data, multiple phase locked loops and multiple reference clocks may be provided. In an integrated circuit with multiple input data ports, the proliferation of multiple phase locked loops and multiple reference clocks may unduly complicate the integrated circuit.